The semiconductor manufacturing industry places an increased emphasis on cost savings to compensate for a constantly dwindling profit margin. Development of high aspect ratio contact etchers requires extremely high ion energy at a substrate surface.
The requirement of using extremely high ion energies in plasma etching processes further complicates the issue of maximizing throughput while minimizing cost of maintenance of plasma reactor parts. Specifically, when high energy ions are used in a reactor to bombard a wafer surface, the inside of the reactor exposed to the plasma is also bombarded with high energy ions, thus increasing the wear rate of the reactor parts.
FIG. 1 is a cross-sectional illustration of a conventional small volume chamber wafer processing system during a conventional small volume chamber etching process. System 100 has a rectangular cross-section that includes a grounded upper confinement chamber portion 102, a grounded lower confinement chamber portion 104, a removable floating confinement ring 108, an electro-static chuck (ESC) 106, a radio frequency (RF) driver 110 connected to ESC 106 and an exhaust portion 114. A plasma-forming space 112 is bounded by ESC 106, grounded upper confinement chamber portion 102, grounded lower confinement chamber portion 104 and removable floating confinement ring 108.
Grounded upper confinement chamber portion 102 is able to be detachably disposed from grounded lower confinement chamber portion 104 at boundary 120, as indicated by the arrow. When detached, removable floating confinement ring 108 may be serviced or replaced, and further, a wafer may be disposed onto ESC 106 for processing.
When a plasma is in contact with a negatively biased surface, such as an electrode or wall, a strong localized electric field appears between the plasma and that surface. This boundary layer, called a “plasma sheath,” is a region of very low electron density, and serves as a medium to accelerate ions from the plasma to the electrode or wall surface. The energy that the ions gain as they are accelerated through plasma sheath regulates both the physical and chemical process at the surfaces surrounding the plasma.
During an etching process, plasma sheath 118 of thickness t1 122 forms between plasma 116 and the surrounding solid surfaces exposed to plasma-forming space 112 (grounded upper confinement chamber portion 102, grounded lower confinement chamber portion 104, removable floating confinement ring 108, and ESC 106). For simplicity in explanation, it is assumed that for small volume wafer processing system 100, the electrode area of ESC 106 is about the same as the electrode area of the grounded surfaces exposed to plasma-forming space 112 (grounded upper confinement chamber portion 102, grounded lower confinement chamber portion 104, and removable floating confinement ring 108). If the relative electrode areas of ESC 106 and the grounded surfaces exposed to plasma-forming space 112 were very different, the plasma sheath between plasma 116 and ESC 106 would be different than that between plasma 116 and the grounded surfaces. The role of electrode areas in determining plasma sheaths will be discussed in more detail later.
In the figure, a wafer 124 is held on ESC 106 via an electrostatic force. A voltage differential is provided between ESC 106 and grounded portions (grounded upper confinement chamber portion 102, grounded lower confinement chamber portion 104, and removable floating confinement ring 108), via RF driver 110, while pressure is decreased in plasma-forming space 112. Further, an etching material is supplied into plasma-forming space 112 via an etching material source (not shown). The pressure within plasma-forming space 112 and the voltage differential, as created by RF driver 110, is set such that the etching material supplied into plasma-forming space 112 creates plasma 116. Plasma 116 etches material within plasma-forming space 112, which includes wafer 124.
As discussed previously, plasma sheath 118 of thickness t1 122 extends between plasma 116 and a bottom surface 126 of grounded upper confinement chamber portion 102, an inner surface 128 of removable floating confinement ring 108, a top surface 130 of grounded lower confinement chamber portion 104, and ESC 106. As RF voltage is applied to electrode 106, plasma is formed and ions within plasma 116 are accelerated through plasma sheath 118 to perform the etching process.
During an etching process, extremely high ion energies are typically needed. Such extremely high ion energies can be achieved by increasing an applied RF voltage to ESC 106 as supplied by RF driver 110. The ion energies of plasma 116 are defined by the potential difference between wafer 124 and plasma 116. Wafer DC bias is related to the electrode area ratio between ESC 106 and grounded upper confinement chamber portion 102, removable floating confinement ring 108 and grounded lower confinement chamber portion 104. DC bias is also directly related to the difference between the potential of plasma 116 with respect to the grounded surfaces (grounded upper confinement chamber portion 102, removable floating confinement ring 108 and grounded lower confinement chamber portion 104) and the potential of plasma 116 with respect to wafer 124. The electrode area and the corresponding wafer DC bias will be discussed in more detail below.
The combined electrode area of the powered electrode with respect to the combined electrode area of the grounded surfaces is conventionally referred to as the electrode area ratio. The electrode area ratio is a function of the areas of the physical surfaces and is also a function of the electrical properties of the materials of the physical surfaces. Using different materials for parts of system 100 may change the electrical properties thereof by changing the impedance between the ESC 106 and grounded upper confinement chamber portion 102, removable floating confinement ring 108 and grounded lower confinement chamber portion 104. In this light, removable floating confinement ring 108 may be removably disposed and replaced with a different confinement ring having different electrical properties and having it either electrically floating or grounded. Such a replacement may change the electrical properties of system 100 thus changing the area ratio and ultimately changing the DC bias between ESC 106 and grounded upper confinement chamber portion 102 and grounded lower confinement chamber portion 104.
High aspect ratio (HAR) etching typically demands extremely high ion energies at the surface of wafer 124, and therefore may require increased driving voltages from RF driver 110, for increased periods of time. These increased driving voltages result in higher plasma potential within plasma-forming space 112 therefore resulting in higher energy ions bombarding the grounded surfaces (bottom surface 126 of grounded upper confinement chamber portion 102, inner surface 128 of removable floating confinement ring 108 and top surface 130 of grounded lower confinement chamber portion 104) as well as the surface of wafer 124.
To minimize the accelerated wear of parts of system 100, the plasma potential, and therefore t1 sheath potential may be adjusted by increasing the electrode area ratio between ESC 106 and the grounded portions, i.e., grounded upper confinement chamber portion 102 and grounded lower confinement chamber portion 104. The electrode area ratio may be increased by increasing at least one of the physical surface area or changing the electrical properties of at least one of grounded upper confinement chamber portion 102 and grounded lower confinement chamber portion 104.
A conventional large volume chamber wafer processing system, which will be discussed in more detail below, has an increased electrode area ratio over the conventional small volume chamber wafer processing system as discussed above. Specifically, the conventional large volume chamber wafer processing system has a much larger plasma-forming space, which is bounded by grounded surfaces, as compared to the plasma-forming space of the conventional small volume chamber wafer processing system. Therefore, the conventional large volume chamber wafer processing system has a much larger grounded surface area as compared to the grounded surface area in the conventional small volume chamber wafer processing system. As such, the conventional large volume chamber wafer processing system has an increased wafer DC bias as compared to the conventional small volume chamber wafer processing system. Large ground-to-powered electrode area ratio not only increases the ion energy at the wafer surface but decreases the plasma potential, and therefore decreases wear rate of grounded chamber parts that face plasma.
An example conventional large volume chamber wafer processing system will now be described with reference to FIG. 2.
FIG. 2 is a cross-sectional illustration of a conventional large volume chamber wafer processing system during a conventional large volume chamber etching process. System 200 includes a grounded upper confinement chamber portion 202, a grounded lower confinement chamber portion 204, a grounded chamber wall portion 208, an ESC 132, and an RF driver 210 connected to ESC 206. A plasma-forming space 212 is bounded by grounded upper confinement chamber portion 202, grounded lower confinement chamber portion 204, ESC 206 and grounded chamber wall portion 208.
A wafer 220 is held onto ESC 206 via an electrostatic force. RF driver 210 provides an RF signal to ESC 206 to create plasma 224, similar to the manner discussed above, in plasma-forming space 212. Plasma sheath 218 of thickness t2 226 exists between plasma 224 and grounded surfaces (grounded upper confinement chamber portion 202, grounded lower confinement chamber portion 204, and grounded chamber wall portion 208). A different plasma sheath (not shown) with a larger thickness exists between plasma 224 and wafer 220, since now the electrode area of the powered electrode (ESC 206) is different from the area of the grounded electrodes. This difference in the plasma sheaths allows for high-energy ions (corresponding to thicker plasma sheath and larger sheath potential) to be provided to the surface of wafer 220 while low-energy ions (corresponding to thinner plasma sheath and smaller sheath potential) to be provided to the grounded chamber portions.
Plasma-forming space 212 includes a first plasma-forming space portion 216, which corresponds to plasma-forming space 112 as discussed above with reference to system 100 in FIG. 1, in addition to plasma-forming space 214. With larger plasma-forming space 212, as compared to plasma-forming space 112, system 200 has a larger grounded surface area as compared to the grounded surface area of system 100. Specifically: grounded upper confinement chamber portion 202 of system 200 has a larger surface area than grounded upper confinement chamber portion 102 of system 100; grounded lower confinement chamber portion 204 of system 200 has a larger surface area than grounded lower confinement chamber portion 104 of system 100; and grounded chamber wall portion 208 of system 200 has a larger surface area than removable floating confinement ring 108 of system 100.
The increased surface area described above provides a larger area ratio between ESC 206 and grounded chamber portions, which in this case include grounded upper confinement chamber portion 202, grounded lower confinement chamber portion 204 and grounded chamber wall portion 208. As mentioned previously, this larger area ratio increases ion energy at wafer 220 while decreasing the potential of plasma 224 with respect to ground and decreasing the thickness t2 226 of plasma sheath 218. The potential of plasma sheath 218 is smaller than the potential of plasma sheath 118, and therefore results in lower ion energy provided to the grounded chamber portions, and thus resulting in lower wear rate. The difference between the potentials of sheath 218 and sheath 118 is related to the difference in the electrode area ratio of system 200 and the area ratio of system 100. Thus system 200 is able to provide less plasma sheath potential (and therefore less ion energy) to its grounded chamber portions than system 100.
The increased ion energy at wafer 220 increases the etch rate of system 200 over system 100. This is the benefit of a conventional large volume chamber as compared to a conventional small volume chamber.
Unlike the conventional small volume chamber shown in FIG. 1, the conventional large volume chamber shown in FIG. 2 does not include a removable floating confinement ring. Therefore, unlike the conventional small volume chamber shown in FIG. 1, the electrical properties of chamber of FIG. 2 may not be readily changed in order to adjust the area ratio and ultimately adjust and optimize the wafer DC bias.
The overall trade off with system 200 of FIG. 2 as compared to system 100 of FIG. 1, is that system 200 has an increase in wafer DC bias over the wafer DC bias of system 100, whereas system 200 has more expensive overall operation and less flexibility with no replaceable floating confinement ring.
What is needed is a chamber wafer processing system that has an increased wafer DC bias over the conventional small volume chamber wafer processing system while providing less operating costs than the conventional large volume chamber wafer processing system.